Various semiconductor or other devices may utilize internally generated data and/or data received from external sources to perform a variety of functions. For example, the devices may include memory devices with internal generator circuits that may be in the form of counters to internally generate data patterns or to internally generate addresses for accessing memory locations. However, these internal generator circuits may encounter timing issues with respect to operational and/or testing modes of the device.
For example, a memory device 12 may be coupled to a memory tester 10 as illustrated in FIG. 1. The memory tester generally tests several memory devices formed on a wafer. The memory device can be in the form of a Dynamic Random Access Memory (DRAM) and may internally generate addresses for the memory device in certain modes. Memory tester 10 typically provides signals to the memory device to perform various tests. These signals are provided to the memory device via a set of pads or pins (not shown), and may be associated with a clock, a command, an address and data. The memory device includes a pad circuit 14 and a compression circuit 16. The compression circuit compresses the received data and data from the memory.
The pad circuit receives address information on a reduced quantity of pads and produces an address for the memory device. The pad circuit may generate an address internally or utilize the address received from the memory tester via the pads. Since fewer pads are needed for each memory device, this configuration enables the memory tester to test a greater quantity of memory devices in parallel. By way of example, the pad circuit may utilize three pads to produce a desired twelve bit address. Since three address bits are received within a clock cycle (e.g., one address bit is received on each pad within a clock cycle), a full twelve bit address is produced after four clocks.
Referring to FIG. 2, once memory device 12 enters a test mode, test commands from memory tester 10 are received. Since an address provided by the memory tester is obtained in four clocks due to the reduced pad configuration, the internally generated addresses are utilized by the memory device during this interval (e.g., prior to the address being available from the address converter). Once four clock periods have expired, the address from the memory tester is utilized. After this period, the internally generated address is utilized until the next address from the memory tester is available (e.g., in four clock cycles).
The memory device should not revert from the externally supplied address to the internally generated address until a falling edge of a test mode signal (e.g., indicating use of the externally supplied address is complete). If the memory device prematurely reverts back to the internally generated address, the incorrect or inappropriate address for the memory device is accessed and the results of the test are corrupted. This may occur even though a proper address may be supplied from the memory tester. Further, utilization of a specific address in test mode may require issuance of several dummy operations that enable the internally generated address to be incremented or otherwise adjusted to the specific address, thereby introducing testing inefficiencies and wasting device resources. Similar scenarios may exist with respect to internally generated data or addresses within other devices.